In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry.
The cells within a CAM array are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary (or quaternary) CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}. A quaterna CAM cell is different from a ternary CAM cell because it has four valid combinations of states: ((data=0, mask=active), (data=1, mask=active), (data=0, mask=inactive), (data=1, mask=inactive)). Quaternary CAM cells are frequently treated as “ternary” CAM cells because two of the four states represent equivalent active mask conditions when search operations are performed. However, ternary CAM (TCAM) cells and quaternary CAM (QCAM) cells will be treated herein as separate categories of CAM cells.
CAM cells may use a variety of different memory cell technologies, including volatile SRAM and DRAM technologies and nonvolatile memory technologies. CAM cells based on these technologies are disclosed in U.S. Pat. Nos. 6,101,116, 6,128,207, 6,256,216, 6,266,263, 6,373,739 and 6,496,399, assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. In addition, U.S. Pat. No. 6,522,562 to Foss, entitled “Content Addressable Memory Cell Having Improved Layout,” discloses a CAM cell that uses p-channel transistors as SRAM access transistors. These p-channel transistors purportedly improve layout efficiency by providing a balanced number of p-channel and N-channel transistors within each CAM cell. In particular, FIG. 4 of the '562 patent illustrates a CAM half-cell that includes a 6T SRAM cell defined by two PMOS access transistors P3 and P4, two PMOS pull-up transistors P1 and P2 and two NMOS pull-down transistors N1 and N2. One half of a 4T compare circuit is also illustrated as including two NMOS transistors N3 and N4. Unfortunately, because PMOS transistors typically have lower mobility relative to equivalently-sized NMOS transistors, using PMOS transistors as access transistors within an SRAM cell may require relatively large PMOS transistors that increase overall unit cell size.
CAM cells having small unit cell size can also be achieved using lower transistor count dynamic CAM cells. For example, FIG. 5 of U.S. Pat. No. 6,188,594 to Ong, entitled “Reduced-Pitch 6-Transistor NMOS Content-Addressable-Memory Cell,” discloses a 6T CAM cell having a non-unity layout aspect ratio.
CAM cells may be configured with NOR-type or NAND-type compare logic. In the case of NOR-type compare logic, a match line associated with a row of CAM cells is typically switched high-to-low upon detection of at least one “miss” in the row during a search operation. NOR-type compare logic typically provides for faster CAM cell operation during search operations with relatively high match line power consumption. Because of the parallel configuration of NOR-type compare logic, parasitic leakage currents through the compare logic transistors may provide a significant pull-down force on a match line and lead to search failure. In contrast, in NAND-type compare logic, a match line signal is propagated across the compare logic and lower match line power is typically consumed. For example, in the conventional ternary NAND-type CAM cell 20 of FIG. 2A. a match line signal may be propagated across at least one of two parallel paths of a four transistor (4T) compare logic circuit when a match condition is present or blocked from propagation when a miss condition is present. A first one of these two parallel paths is defined by transistor NA, which is responsive to a data signal (DX) applied during a search operation, and transistor NB, which is responsive to a signal generated at a storage node of an X memory cell (SRAM SX). A second one of these two parallel paths is defined by transistor NC, which is responsive to a data signal (DY) applied during a search operation, and transistor ND, which is responsive to a signal generated at a storage node of a Y memory cell (SRAM SY). Unfortunately, because CAM cells having the NAND-type compare logic illustrated by FIG. 2A require serial propagation of match line signals, NAND-type CAM devices are typically slower in operation relative to NOR-type CAM devices. This serial propagation of a match line signal is demonstrated by the pair of NAND-type CAM cells 20′ of FIG. 2B. This pair of CAM cells 20′ includes a left cell containing transistors NA1, NB1, NC1 and ND1 and a right cell containing transistors NA2, NB2, NC2 and ND2. A worst case propagation of a match line signal ML from the left of the left cell to the right of the right cell requires a propagation through four serially-connected transistors NA1, NB1 (or NC1, ND1) and NA2, NB2 (or NC2, ND2). Because of this configuration of conventional NAND-type CAM cells, which may require long serial paths for match line propagation in wide CAM arrays, there exists a need for NAND-type CAM devices having higher speed characteristics while retaining low power characteristics.